1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly, to an output buffer circuit for a semiconductor device.
2. Description of the Related Art
An output buffer circuit in a semiconductor device is used to output internal data through an output terminal or output pad. As shown in FIG. 1, a contemporary output buffer circuit typically includes: an output driver 11 including a pull-up PMOS transistor P11 and a pull-down NMOS transistor N11; an inverter 13 for inverting data to be output, for feeding the inverted data to the gate of the pull-up PMOS transistor P11, and for adjusting the pull-up slew rate of the output driver 11; and an inverter 15 for inverting the output data, for feeding the inverted data to the gate of the pull-down NMOS transistor N11, and for adjusting the pull-down slew rate of the output driver 11.
In the contemporary output buffer circuit as shown in FIG. 1, the slew rate of the output driver 11 is determined by the current that charges the load capacitance C of the output terminal 17 through the pull-up PMOS transistor P11, and the current that is discharged from the load capacitance C of the output terminal 17 through the pull-down NMOS transistor N11. Here, the current varies drastically with process, voltage and temperature (hereinafter referred to as PVT) and the slew rate of the output driver 11 varies drastically with the change of the PVT.
The slew rate of the output driver 11 also varies with the load capacitance C of the output terminal 17. For example, if the load capacitance of the output terminal 17 doubles, the slew rate will change proportionally.
Therefore, the disadvantage of the contemporary output buffer circuit shown in FIG. 1 is that it cannot meet tight slew rate specifications if the PVT and the load capacitance of the output terminal 17 change.
To address the above-described problems, it is an object of the present invention to provide an output buffer circuit that reduces the slew rate variation caused by the change of PVT (process, voltage and temperature) and load capacitance of an output terminal.
Another objective of the present invention is to provide a semiconductor device containing an output buffer circuit that reduces the slew rate variation caused by the change of PVT and load capacitance of the output terminal.
To address the above-described limitations, an output buffer circuit according to the present invention includes: a pull-up driver for pulling up an output terminal in response to a pull-up signal; a pull-down driver for pulling down the output terminal in response to a pull-down signal; a first slew rate control circuit for pulling down the voltage of the pull-up signal in multiple stages in response to a first control signal; and a second slew rate control circuit for pulling up the voltage of the pull-down signal in multiple stages in response to a second control signal.
Preferably, the first slew rate control circuit includes: a first delay circuit for delaying the first control signal in response to a first bias voltage and a second bias voltage; and a first control circuit for pulling down the pull-up signal in response to the first control signal and the second bias voltage in a first stage, and again pulling down the pull-up signal in response to the first control signal and the output signal of the first delay circuit in a second stage.
Preferably, the second slew rate control circuit includes: a second delay circuit for delaying the second control signal in response to the first bias voltage and the second bias voltage; and a second control circuit for pulling up the pull-down signal in response to the second control signal and the first bias voltage in the first stage, and again pulling up the pull-down signal in response to the second control signal and the output signal of the second delay circuit in the second stage.
Preferably, the first bias voltage and the second bias voltage are provided by a phase locked loop (PLL) circuit.
To achieve another objective, the semiconductor device according to the present invention includes: a PLL circuit including a voltage controlled oscillator that outputs a first bias voltage and a second bias voltage; a slew rate control circuit controlled by the first bias voltage and the second bias voltage, for pulling down the voltage of a pull-up signal in multiple stages in response to a first control signal, and pulling up the voltage of a pull-down signal in multiple stages in response to a second control signal; and an output driver for pulling up an output pad terminal in response to the pull-up signal and pulling down the output pad terminal in response to the pull-down signal.
The slew rate control circuit includes: a first slew rate control circuit controlled by the first bias voltage and the second bias voltage, for pulling down the voltage of the pull-up signal in multiple stages in response to the first control signal; and a second slew rate control circuit controlled by the first bias voltage and the second bias voltage, for pulling up the voltage of the pull-down signal in multiple stages in response to the second control signal.
Preferably, the first slew rate control circuit includes: a first delay circuit for delaying the first control signal in response to the first bias voltage and the second bias voltage; and a first control circuit for pulling down the pull-up signal in response to the first control signal and the second bias voltage in a first stage, and again pulling down the pull-up signal in response to the first control signal and the output signal of the first delay circuit in a second stage.
Preferably, the second slew rate control circuit includes: a second delay circuit for delaying the second control signal in response to the first bias voltage and the second bias voltage; and a second control circuit for pulling up the pull-down signal in response to the second control signal and the first bias voltage in the first stage, while again pulling up the pull-down signal in response to the second control signal and the output signal of the second delay circuit in the second stage.
Preferably, the first delay circuit and the second delay circuit comprise unit delays that are substantially similar to unit delays of the voltage controlled oscillator of the PLL.